1. general description the 74ahc157-q100; 74ahct157-q100 is a high-speed si-gate cmos device and is pin compatible with low-power schottky ttl (lsttl). it is specified in compliance with jedec standard no. 7a. the 74ahc157-q100; 74ahct157-q100 is a q uad 2-input multiple xer which selects 4 bits of data from two sources under the cont rol of a common data select input (s). the enable input (e ) is active low. when e is high, all of the outputs (1y to 4y) are forced low regardless of all other input conditions. moving the data from two groups of registers to four common output buses is a common use of the 74ahc157-q100; 74ahct157-q100. the state of the common data select input (s) determines the particular register from which the data comes. it can also be used as function generator. the device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. the 74ahc157-q100; 74ahct157-q100 is logic implementation of a 4-pole, 2-position switch. the logic levels applied to s, determines the position of the switch. the logic equations are: 1y = e ?? (1i1 ?? s+1i0 ?? s ) 2y = e ?? (2i1 ?? s+2i0 ?? s ) 3y = e ?? (3i1 ?? s+3i0 ?? s ) 4y = e ?? (4i1 ?? s+4i0 ?? s ) this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have a schmitt-trigger action ? inputs accept voltages higher than v cc ? multiple input enable for easy expansion ? ideal for memory chip select decoding ? input levels: ? for 74ahc157-q100: cmos level ? for 74ahct157-q100: ttl level 74ahc157-q100; 74ahct157-q100 quad 2-input multiplexer rev. 1 ? 4 july 2013 product data sheet
74ahc_ahct157_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 4 july 2013 2 of 17 nxp semiconductors 74ahc157-q100; 74ahct157-q100 quad 2-input multiplexer ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74AHC157D-Q100 ? 40 ? cto+125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74ahct157d-q100 74ahc157pw-q100 ? 40 ? cto+125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 74ahct157pw-q100 74ahc157bq-q100 ? 40 ? cto+125 ? c dhvqfn16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 ? 3.5 ? 0.85 mm sot763-1 74ahct157bq-q100 fig 1. logic diagram fig 2. logic symbol 1y 1i1 1i0 2y 2i1 2i0 3y 3i1 3i0 mna484 4y 4i1 4i0 s e mna481 s 1 15 12 9 7 4 131410116532 e 1y 1i11i0 2y 2i12i0 3y 3i13i0 4y 4i14i0
74ahc_ahct157_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 4 july 2013 3 of 17 nxp semiconductors 74ahc157-q100; 74ahct157-q100 quad 2-input multiplexer 5. pinning information 5.1 pinning fig 3. logic symbol fig 4. iec logic symbol mna483 multiplexer outputs selector 1y 2y 3y 4y 12 9 7 4 s 13 15 1 14 10 11 6 5 3 2 e 1i0 1i1 2i0 2i1 3i0 3i1 4i0 4i1 mna482 12 9 7 1 g1 15 en 1 mux 1 4 13 14 10 11 6 5 3 2 (1) this is not a supply pin. the substrate is attached to this pad using conductive die attach material. there is no electrical or mechani cal requirement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 5. pin configuration so16, tssop16 fig 6. pin configuration dhvqfn16 $ + & |